1. Field of the Invention
The present invention relates in general to an input circuit for a semi-conductor device, and more particularly to an undershoot resisting input circuit for a semi-conductor device wherein a high voltage of an external input previously applied to the device is isolated and held with no loss at an internal holding node in the device even though the external input is undershot below a ground voltage when it is isolated from the device.
2. Description of the Prior Art
Generally, in the even that a compatible transistor logic (TTL) is employed as external input means for a semi-conductor device, the data specification for all products prescribes for the criteria of an input low voltage that an external input to the device may be undershot at a voltage lower than a ground voltage for a certain period of time. Namely, in a case of 1M dynamic RAM (DRAM) it is allowed that the external input is undershot at -1 V for a time period not exceeding 20 ns and in another case of that it is also allowed that the external input is undershot at -3 V during a time period not exceeding 10 ns.
A conventional input circuit for a semi-conductor device, as shown in FIG. 1, comprises a n-channel MOSFET MT and a parasitic capacitor CL connected to an internal holding node an in the semi-conductor device.
The n-channel MOSFET MT has a gate for inputting an address input signal .PHI.AI, a drain connected to an external input An for the semi-conductor device and a source connected to the internal holding node an.
In operation, if the address input signal .PHI.AI is high with respect to a power supply Vcc, the n-channel MOSFET MT is turned on, thereby enabling the external input An to be transferred to the internal holding node an. The external input An has a value no lower than 2.4 V, or the minimum value of an input high voltage of the TTL. It is also assumed that the external input An is regarded as a high state in a buffer circuit in the semi-conductor device.
When the address input signal .PHI.AI goes low, the n-channel MOSFET MT is turned off, thereby causing the internal holding node an in the semi-conductor device to be isolated from the external input An, so as to prevent external noise from incoming thereinto. At this time, the high voltage of the external input An previously transferred is held at the internal holding node an due to charges on the parasitic capacitor CL. Supposing that the external input An is undershot at -3.0 V, a gate-source voltage of the n-channel MOSFET MT is 3 V (VGS=VG-VS=0-(-3)) enabling the n-channel MOSFET MT to be turned on, thereby causing the internal holding node an to be connected to the external input An. This connection of the internal holding node an to the external input An causes the high voltage held at the internal holding node an to be lost and thus results in a mis-operation of the semi-conductor device.
A conventional undershoot resisting input circuit, as shown in FIG. 2, has been employed in the semi-conductor device as a means for preventing the loss of the voltage at the internal holding node due to the external noise in question in the above-mentioned conventional input circuit.
The conventional undershoot resisting input circuit as shown in FIG. 2 has been employed for a 1M DRAM available from TOSHIBA Co., Ltd.
The conventional undershoot resisting input circuit comprises n-channel MOSFETs M1 to M3 and capacitors C1 and C2.
The n-channel MOSFETs M2 and M3 are connected in series to each other between the external input An and the internal holding node an and include a common gate for inputting the address input signal .PHI.AI. One end of the capacitor C1 is connected to the power supply Vcc and the other end is connected to a common node 1 of the n-channel MOSFETs M2 and M3. The common node 1 is formed by the connection of a source of the n-channel MOSFET M2 with a drain of the n-channel MOSFET M3. On the other hand, one end of the capacitor C2 is connected to the power supply Vcc and the other end is connected to the internal holding node an. A gate of the n-channel MOSFET M1 is connected to the internal holding node an, a drain thereof is connected to the power supply Vcc and a source thereof is connected to the common node 1 of the n-channel MOSFETs M2 and M3.
In operation, if the external input An becomes high or 2.4 V or more during a time period that the address input signal .PHI.AI is high, the n-channel MOSFETs M2 and M3 are turned on, thereby causing the internal holding node an to become high. When the address input signal .PHI.AI goes low under the condition that the internal holding node an holds its high state, the n-channel MOSFETs M2 and M3 are turned off, thereby causing the internal holding node an to be isolated from the external input An, so as to prevent an external noise from incoming thereinto. As a result, the internal holding node an holds its high state. On the other hand, supposing that the external input An is undershot by up to -3 V, a gate-source voltage of the n-channel MOSFET M2 is 3 V (VGS=VG-VS=0 (-3)) enabling the n-channel MOSFET M2 to be turned on, thereby causing the common node 1 of the n-channel MOSFETs M2 and M3 to discharge. This discharging of the common node 1 of the n-channel MOSFETs M2 and M3 is subject to a resistance which results from a delaying effect of the capacitor C1 and an inflow of a charging current through the n-channel MOSFET M1 turned on depending on the high voltage at the internal holding node an. Since the discharging of the common node 1 due to the undershoot of the external input occurring during a certain time period is not sufficient, the n-channel MOSFET M3 is prevented being turned on and the loss of the high voltage at the internal holding node an is thus prevented. The coupling of the capacitor C2 between the gate and the source of the n-channel MOSFET M1 turned on during the discharging of the common node 1 of the n-channel MOSFETs M2 and M3 has the effect of preventing a voltage drop across the internal holding node an. that a leakage current is caused by the series connection of the n-channel MOSFETS M2 and M3 during the undershoot of the external input. The conventional undershoot resisting input circuit has another disadvantage, in that the connection of the capacitor C2 to the internal holding node an results in an increase in load capacitance during the undershoot of the external input.